Referring to FIG. 1, traditionally the circuit topology for heartbeat detection circuit 10 known to the prior art consists of a low noise instrumentation amplifier (IA) 14, an anti-alias filter 18, an analog-to-digital converter (ADC) 22, and a digital signal processor (DSP) or microcontroller 26. This topology is generally employed in a wearable clinical heart monitor.
In this topology, the IA 14 amplifies the differential Electrocardiogram (ECG) signal derived from patient electrodes, using low noise operational amplifiers (op-amps) to minimize the addition of circuit noise. The gain of the IA 14 is set so that the amplified output is not saturated. The output signal from the IA next passes through the anti-alias filter 18, and then the ADC 22 uniformly quantizes the ECG signal, treating small features such as ECG's P wave and large features such as ECG's R wave with equal resolution. The ADC 22 is usually implemented with a medium resolution successive approximation register (SAR) architecture to minimize power consumption. Finally, to detect heartbeats, the digitized ECG is processed by the microprocessor 26 using a peak detection algorithm to detect R-waves. Depending on the computational power of the available microprocessor or DSP 26, such an algorithm ranges from a simple thresholding algorithm to one employing wavelet transforms.
This traditional topology is necessary for clinical ECG measurements, where multilead or multielectrode ECG signals are acquired with high quality in order to diagnose complex arrhythmias. These recordings are usually quantized with at least 12 bits to preserve the finer details of the P wave of the ECG. The American Heart Association recommends that the ADC use a sampling frequency of at least 150 Hz to capture all features, while stating that a bandwidth of 1 Hz to 30 Hz generally produces a stable ECG without digitization artifacts.
However, for applications employing the wearable heart monitor, generally only the R-wave timing is relevant. What is needed is a monitor that will provide this timing while removing the need for ADC and signal processing and thereby significantly decreasing the circuit's power requirements and size while robustly extracting heartbeat timings in the presence of motion artifacts and degraded signal quality.
The present invention addresses this need using a new topology for the heartbeat detection circuit.